发明名称 ADDRESS EXTENDING SYSTEM
摘要 PURPOSE:To extend an address by adding a register to hold the upper bits of an extended index, and controlling the mode of extension by the ON/OFF state of an extended display bit of an extended base register designated by an instruction word. CONSTITUTION:The extended base addresses of base addresses BSH, BSM and BS, the extended indexes of indexes IXH, IXM and IX and a displacement DP of 12 bits are added 10 together regardless of modes and registered 11. Bits 40- 63 of the register 11 are stored as they are in an effective address register EAR of a register 9. While bits 32-39 are stored in the register EAR of the register 9 by a medium bit selecting circuit 12 in the case of E=1 (new mode) with the extended base register. The register EAR is set at 0 with E=0. A selecting circuit 17 selects bits 8-31 with E=1 and E=0 of the register 11. This facilitates an easy extension of address.
申请公布号 JPS5981742(A) 申请公布日期 1984.05.11
申请号 JP19820192046 申请日期 1982.11.01
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 TAJIRI KAZUO
分类号 G06F9/34;G06F9/355;G06F12/02;G06F12/10 主分类号 G06F9/34
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