| 摘要 |
<p>A microcontroller for controlling a digital device without loss of clock cycles which controller is formed of a plurality of control stores (20a, 20b, 20c) each of which is provided with a register counter (21a, 21b, 21c) to address different locations within corresponding control store. Each control store is accessed each clock cycle and an instruction register (22) is provided to receive one of the fetched microinstructions from the selected control store. In this manner, a microinstruction is presented to the instruction register each clock cycle even though the previous microinstruction was a conditional branch, a jump to subroutine or a return to subroutine instruction. In order to accommodate jump to subroutine and corresponding return from subroutine instructions, arbitration logic (27) is provided to specify which control store is to provide the next microinstruction of the routine to which the jump is made and also which control store is to provide the next microinstruction after that routine is completed. </p> |
