发明名称 |
Circuit arrangement for monitoring electronic computer chips |
摘要 |
A circuit arrangement for monitoring electronic computer chips is proposed which output periodic signals at one of their outputs when operating correctly. Two series-connected retriggerable timing sections (11, 14) trigger a signal generator stage (15) which is preferably constructed as a timing section and which generates a reset signal for the computer chip (10). The periodic signals trigger the first timing section (11) which sets a minimum permissible signal spacing whilst the second timing section (14) sets a maximum permissible signal spacing. To be able to generate a sequence of reset signals even when the signal sequence (U10) is too fast, these are additionally supplied to the trigger input of the second timing section (14). <IMAGE>
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申请公布号 |
DE3240704(A1) |
申请公布日期 |
1984.05.10 |
申请号 |
DE19823240704 |
申请日期 |
1982.11.04 |
申请人 |
ROBERT BOSCH GMBH |
发明人 |
FISCHER,WERNER;GERHARDS,GERD;HASSLER,ALBIN |
分类号 |
G06F11/00;(IPC1-7):G06F11/22 |
主分类号 |
G06F11/00 |
代理机构 |
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主权项 |
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