| 摘要 |
PURPOSE:To obtain an arithmetic device of high performance with a simple constitution by providing an arithmetic circuit which uses plural multipliers to perform simultaneously the processing for coefficients of adjacent filters and the addition processing with the result of the preceding processing. CONSTITUTION:The original picture data Gi and (j) are latched by original picture data latches 5A and 5B; and at the same time the 1st and the 2nd filter coefficient data are latched by coefficient data lathes 5C and 5D respectively. Then the output of the processed picture data latch 50 supplied via a data bus line l12 is multiplied 5F by the output of the latch 5A. At the same time, the output of the latch 5D supplied via the line l12 is multiplied 5G by the output of the latch 5B. These outputs of multipliers 5F and 5G added 5H together, and the output of the addition 5H is added 5I to the output of a latch 5E supplied via the line l12. As a result of this addition result, the picture data is latched 5J. In such a way, it is possible to obtain an arithmetic device of space filter with which the address control is easy with a high processing speed and high general-purpose properties. |
