| 摘要 |
PURPOSE:To omit an oridinarily required A/D converter and to save a memory by providing a means comparing an image signal delayed by one clock with an image signal before the delay. CONSTITUTION:The 1st sample holding circuit 1 samples and holds an image signal IG from a picture sensor and an operational amplifier 5 discriminates whether the image signal IG is at the prescribed level or not, and when more than the prescribed value, supplies the output to a JK FF 6 as a clock signal. On the other hand, the output of the amplifier 5 is delayed by one sampling period by a delay device 7 and the delayed output opens an analog switch 8, so that the contents of the sample holding circuit 1 are delayed by one clock signal period and sampled and held in a sample holding circuit 2. The outputs of both the sample holding circuits 1, 2 are compared by comparators 3, 4 successively, and every inversion of the output, the counted value of a counter 9 is stored in an RAM 12. |
