发明名称 READ ONLY MEMORY ARRAY
摘要 PURPOSE:To improve the general-purpose property and the secrecy holding property by a method wherein a MOSFET having a MOSFET and a floating gate electrode is selectively arranged between a word line and a bit line. CONSTITUTION:The MOSFET's 11-35 are arranged between the word lines 1-5 and the bit lines 6-10. The word lines 1-5 are connected to gates of the FET's 11-35, and the bit lines 6-10 are selectively connected to drains. Some of the MOSFET's 11-35 have normal FET's and floating gate electrodes: one having a floating gate electrode like the FET11 can be put in non-conduction by electron implantation. For example, when the word line 1 and the bit line 6 are put at a high potential, the bit line 6 can be put both at a high potential and at a low potential. Therefore, also after completing the array, the memory content becomes variable and then the general-purpose property improves.
申请公布号 JPS5978562(A) 申请公布日期 1984.05.07
申请号 JP19820188710 申请日期 1982.10.27
申请人 NIPPON DENKI KK 发明人 YASUDA SADAHIRO
分类号 G11C16/04;G11C17/00;H01L21/8246;H01L21/8247;H01L27/112;H01L29/788;H01L29/792 主分类号 G11C16/04
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