| 摘要 |
PURPOSE:To attain the high speed by a digital circuit without increasing a clock frequency, by setting a sampling pulse frequency based on a biphase code pulse width and a standard pulse width. CONSTITUTION:A differential Manchester code signal 201 is applied to a D input of an FF101 and an asynchronous sampling pulse 202 of T/6 to a bit period T of the input signal 201 is applied to a C input respectively, the pulse 202 is applied to the C input of DFF102, 104 and a counter 106. The frequency of the pulse 202 is set by obtaining the difference between the maximum value of the pulse width of the signal 201 to be discriminated as T/2 and the standard pulse width T, and the difference between the minimum pulse width of the signal 201 to be discriminated as the period T and the standard pulse width T/2, and maximizing the smaller difference. As a result, a decoding clock signal 203 and a decoding data signal 204 are obtained. |
