发明名称 DATA BUFFER CONTROLLING SYSTEM
摘要 PURPOSE:To perform the buffer control efficiently by using an address indicated by a read address register for the read from a data buffer to share one data buffer management method between forward channel instructions and read backward instructions. CONSTITUTION:Write and read address counters 11 and 12 designate write and read word addresses of a data buffer 14 respectively. A read address register 16 which designates a read address of the data buffer for a read backward instruction and a control circuit 20 are provided. The buffer 14 is managed by the differential value between write and read address counters 12 and 11 when a forward channel instruction is executed, and the buffer 14 is managed similarly to the management for the forward channel instruction when a read backward instruction is executed. The address indicated by the register 16 is used for the read from the buffer 14. Thus, one buffer management method is shared between both channel instructions.
申请公布号 JPS5977535(A) 申请公布日期 1984.05.04
申请号 JP19820185522 申请日期 1982.10.22
申请人 FUJITSU KK 发明人 MATSUZAKI SHIGEHARU
分类号 G06F13/12;G06F3/00;G06F3/06;(IPC1-7):06F3/00 主分类号 G06F13/12
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