| 摘要 |
PURPOSE:To decrease the processing time and to simplify the processing program by providing a means setting >=2 memory blocks into the operating state at the same time and reading or writing the data to a prescribed block to the blocks. CONSTITUTION:An address bus 90 of a CPU 100 is connected to RAMs 150, 160, and ROMs 170, 180 to which the same address is set in each block, and the readout data from the RAMs 150, 160 and the ROMs 170, 180 to the CPU 100 via data buffers 42-45 and a data bus 80. The address of the bus 90 is decoded by a decoder 206 and each memory block is selected by an address decode signal 1000. Data latches 33, 300 are connected to a data latch signal line 70 to decode the selecting data from the latch 300 at a decoder 400 and to select one of each memory block. Thus, the processing time is decreased and the processing program is simplified. |
