| 摘要 |
PURPOSE:To reduce the reduction in unnoticed rate by means of a frame check sequence, by making a bit pattern frame representing the start of the frame effective only when a specific pattern continues for a prescribed number or over. CONSTITUTION:A frame and a time fill pattern are applied from a terminal A to a shift register SR1. DFF3-5 invert an output Q in synchronizing with a clock from a terminal C, each output of exclusive OR circuis 6, 7, and an AND circuit 8 goes to ''1'', the counter 10 keeps advancing and a JKFF11 is set. Further, the frame is transmitted from an SR1 to a comparator 2, and compared 2 with an FS pattern from a terminal B. When the result of comparison is coincident, ''1'' is given to an AND circuit 12 to inform the detection of FS. Thus, ''1'' is transmitted from the FF11 so as to inform that the FS is effective. |
