发明名称 |
VERFAHREN ZUM HERSTELLEN EINER INTEGRIERTEN SCHALTUNG MIT EINER DUENNEN ISOLIERSCHICHT |
摘要 |
A method for delineating thin layers of material, e.g. thin oxide layers, is disclosed. A protective layer of electrically conductive material (60), e.g. of polysilicon, is deposited onto the thin layer of material (30) in order to protect the thin layer against any contamination and/or erosion which might occur during subsequent lithographic processing. The protective layer of material is then patterned, e.g. by means of a resist layer (70) in order to delineate the thin layer of material. The method is particularly suited to forming source and drain contact holes in the gate oxide of FETs, by etching a hole or holes through the thin layer (30) and depositing a further electrically conductive material onto the unmasked protective layer and into the hole(s). <IMAGE> |
申请公布号 |
DE3339268(A1) |
申请公布日期 |
1984.05.03 |
申请号 |
DE19833339268 |
申请日期 |
1983.10.28 |
申请人 |
WESTERN ELECTRIC CO.,INC. |
发明人 |
NELSON FULS,ELLIS;JOSEPH LEVINSTEIN,HYMAN |
分类号 |
H01L29/78;H01L21/033;H01L21/28;H01L21/306;(IPC1-7):01L21/82;01L21/32 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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