| 摘要 |
<p>Method of fabricating a semiconductor device in which method a layer of an electrically conductive material is evapor deposited on a general plane of a semiconductor chip. The layer is deposited in two steps, initially with an average deposition rate R1 which is not greater than 1 nm/s, and subsequently with an average deposition rate R2 which is greater than 2R1. Continuity defects such as tunneling, thinning and microcracking in the layer as reduced, while the method nearly achieves the throughput of prior art methods. </p> |
