SELF-ALIGNED METAL PROCESS FOR INTEGRATED CIRCUIT METALLIZATION

摘要

SELF-ALIGNED METAL PROCESS FOR INTEGRATED CIRCUIT METALLIZATION A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive FI9-80-010 ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. FI9-80-010