发明名称 TESTING SYSTEM OF CENTRAL PROCESSING UNIT
摘要 PURPOSE:To send out easily a fault state simulating signal by selecting plural data generating circuits which are arrayed optionally, in accordance with the number of times of a simple access signal transmitted from an interface part of a tester. CONSTITUTION:An interface circuit 21 sends out ''1'' as an access signal to a counting circuit 22, executes counting and sends out an output signal to a decoding cicuit 23. For instance, a data generating circuit 24a is selected, and a fault state simulating signal which said circuit sends out is sent out to a body to be tested CPU (DUT) 1 through the circuit 21. The DUT1 processes it by a fault countermeasure function and gives an answer to the circuit 21. The circuit 21 decides or records whether the answer is good or not, and makes preparations for sending out the following signal. In this way, a tester for testing the fault countermeasure function of the DUT1 can be constituted by sending out the access signal from the interface circuit 21 and selecting successively or optionally the data generating circuits 24a-24n.
申请公布号 JPS5975345(A) 申请公布日期 1984.04.28
申请号 JP19820185517 申请日期 1982.10.22
申请人 FUJITSU KK 发明人 ADACHI YUUTA
分类号 G06F11/22 主分类号 G06F11/22
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