| 摘要 |
PURPOSE:To reduce the number of elements by making a cascade connection so that the output signal of a logical gate is supplied as a clock signal to the next unit stage, supplying a reset signal to all stages prior to presetting operation, and then supplying a preset enable signal. CONSTITUTION:When a clock CL signal supplied to a unit stage 210 through an NAND gate 200 is at ''H'', CL signals of all trailing stages are ''H''. Therefore, a reset signal and a preset enable signal supplied to each unit stage are supplied to input terminals of the gate 200 to fix the CL signal of each stage at ''H'' in a reset or preset period; and two-way switches 16 and 18 are open and 13 and 17 are closed in said period, so the reset or preset signal is supplied to only a bistable circuit 250 to reset or preset each stage. Further, the command of resetting, etc., is released after the CL at a terminal 90 has changed to ''L'', so that a counter never malfunctions. |
