| 摘要 |
The present invention relates to a charge-transfer analog delay line. The delay line according to the invention includes a charge-transfer shift register 1 receiving samples of the analogue input signal E(t) to be delayed and containing N stages e1 to eN, a means of digital coding 2 with N outputs permitting a single output to be addressed depending on the address given as input, charge-reading means L1 to LN at the level of each stage of the shift register and means C1 to CN of controlling the reading means L1 to LN which are each triggered by one of the outputs Bk of the coding means 2 so as to obtain at output the signal originating from one of the stages of the shift register 1. The invention applies, for example, to sonars, radars, etc. <IMAGE>
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