| 摘要 |
PURPOSE:To obtain a high S/N with a small number of frequency jitters when a frequency divider is used to a PLL, by regarding the divider as a normal fixed frequency divider within an allowable range of phase errors. CONSTITUTION:An input is supplied to a variable frequency divider 10 from the 1st input 8 and switched among 3-, 5- and 7-divisions by outputs 13a and 13b and outputs 10-11. The 2nd input 9 is equal to a pulse width modulated signal. When the phase of this modulated signal advances, the dividing ratio is set at 7 and then at 3 when the phase delays. When the pulse width modulated signal has a phase within a prescribed range, the dividing ratio is set at 5. A period during which the dividing ratio is set at 3 or 7 is set equal to the output cycle of a fixed frequency divider 12. The figure 11 shows a fixed frequency divider. |
