| 摘要 |
PURPOSE:To enable to largely set the ratio of selected current to hold current by a method wherein an FF circuit composed of a bi-polar type drive transistors, clamp elements, and load MOSFET's is used for a memory cell. CONSTITUTION:For the memory cell, the FF circuit composed of the dive N-P-N transistors TR Q5 and Q6, whose bases and collectors are cross-connected each other, the voltage clamping Schottky diodes SD1 and SD2 provided in the collectors, and the load P-channel MOSFET's Q7 and Q8 provided respectively in parallel with these SD1 and SD2, and whose gates are connected each to the other TRQ6 and Q5 is used. Such a constitution enables to largely set the ratio of the selected current Ir flowing to a complementary data line D0 and an inversion D0 to the hold current flowing to a common emitter circuit of the TR's Q5 and Q6. As a result, high speed actions and large memory capacitance can be realized. |
