DATA INTERFACE MECHANISM FOR INTERFACING BIT-PARALLEL DATA BUSES OF DIFFERENT BIT WIDTH

摘要

Data interface mechanism for interfacing an M-byte data bus (34a, 34b) with an N-byte data bus (37), where M is a multiple of N. The invention provides an automatic mechanism for converting M-byte data segments into N-byte data segments and vice-versa. A number of storage units (22a and 22b) are located intermediate the M-byte and the N-byte data buses, the number of storage units being equal to the ratio of M to N and each such storage unit having a width of N-bytes. The storage units are accessed one at a time in a rotating manner for transferring N-byte data segments between the N-byte data bus and different ones of the storage units. All the storage units are simultaneously accessed for transferring M-byte data segments between the M-byte data bus and the storage units.