发明名称 MEMORY DEVICE
摘要 PURPOSE:To write quickly many same data, by making all chip selecting signals active independently of a part of an address by a decoder decoding a part of the address to the chip selecting signal. CONSTITUTION:A decoder 2A makes sequentially the chip selecting signals S10 S13 active in response to the input of a part of the address, and data are written sequentially in corresponding memory elements M1-M4. On the other hand, in setting an FF3 and applying a high level Q output to the decoder 2A, the decoder 2A makes all of the signals S10 S13 active independently of a part of the address, the same data are written in the memories M1-M4 at the same time, and the write of many same data is attained quickly.
申请公布号 JPS5972693(A) 申请公布日期 1984.04.24
申请号 JP19820182501 申请日期 1982.10.18
申请人 TOSHIBA KK 发明人 TANIMOTO ITARU
分类号 G11C11/413;G06F12/00;G06F12/06;G11C7/00;G11C11/41 主分类号 G11C11/413
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