发明名称 DATA PROCESSOR
摘要 PURPOSE:To perform simultaneously both reading and writing for a series of operations and to make the processing high speed by writing the result obtained by reading the data out of one of plural memories and then calculating it into a memory other than that which read out said data. CONSTITUTION:Memories 1 and 2 are switched alternately under the control of a memory control circuit 7, and the digigal signal obtained by giving A/D conversion to the supplied video signal is written to either one of memories 1 and 2 via an adder 2. While the signal is read out of the other memory at a time and then added 2. Thus a mask image for subtraction is formed. The output of the adder 2 divides 3 another signal and stores a mask for subtraction in a memory 3. Then a subtraction 4 is carried out between the output of the divider 3 and the output of the memory M3, and the result of this subtraction is delivered in the form of a display signal. In the same way, the writing and reading are repeated alternately by means of an adder 5 and memories M4 and 5 to perform an addition 5 with a division 6 carried out with another signal. Thus a display output is produced, so that the data processing speed is accelerated.
申请公布号 JPS5972549(A) 申请公布日期 1984.04.24
申请号 JP19820182800 申请日期 1982.10.20
申请人 TOSHIBA KK 发明人 SUZUKI WATARU;NAKAYAMA NOBUTOSHI
分类号 G01N23/04;A61B6/00;G01T1/161;G06F12/00;G06F12/06;G06F13/00;G11C7/00;H04N5/91 主分类号 G01N23/04
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