发明名称 DIAGNOSING CIRCUIT OF SAMPLE TIME CLOCK SIGNAL
摘要 PURPOSE:To have a quick diagnosis of a fault, by storing the output signals of cascaded timers with the sample time clock signal and then diagnosing the timing of generation of the sample time clock signal. CONSTITUTION:A sample time clock (STC) signal (a) having a cycle T is always supplied to an input terminal 3a and then applied to a timer 1a which is driven at the rear edge of the signal (a). The timer 1a generates a signal (b) having a continuous time T1, and this signal (b) is transmitted through a timer 1b to produce a signal (c) having a continuous time T2. This time T2 of the signal (c) is set within a period of a normal STC signal. The signal (c) is fed to a storage circuit 2 to decide whether the STC signal is within the time T2. If the signal (a), for example, lacks, an output signl (g) of a period T3 is delivered when a normal STC signal (a) is supplied. Thus a fault is diagnosed.
申请公布号 JPS5972519(A) 申请公布日期 1984.04.24
申请号 JP19820184195 申请日期 1982.10.20
申请人 YAMATAKE HONEYWELL KK 发明人 SHIMIZU HIDEYUKI;ENAMI KOUZOU
分类号 G05B23/02;G06F11/00;G06F11/22 主分类号 G05B23/02
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