| 摘要 |
PURPOSE:To realize a memory with a high speed and low power consumption without increasing chip area, by driving the word line of a partial memory cell group by an AND gate output. CONSTITUTION:High-order row address information inputted to a high-order address signal line 5a is decoded by a high-order row decoder 4a to activate one of high-order row selecting lines 3a arranged at each two-row. On the other hand, a sub-decoder 17 decode both the high-order column address information and the low-order row address information and selects one of the partial memory cell groups 12a-12d and one of the two rows. An AND gate 19 generates the logical product between the high-order row selecting signal and the sub- decoder output to activate only one word line 3 of one block. Thus, the memory cell group to be accessed is discriminated. |
