| 摘要 |
PURPOSE:To eliminate a negative DC bias generated at signal processing without increasing the number of adders, by providing a multiplier and an adder/subtractor and adding 1 to the least significant bit by the adder/subtractor when the result of multipliation of the multiplier is negative. CONSTITUTION:The multiplier 1 multiplies the 1st multiplier in 4-bit given to input terminals A1-A4 with the 2nd multiplier in 4-bit given to input terminals B1-B4 in the complemental expression of 2. The high-order 4-bit as the result of multiplication is given to the input terminals B1-B4 of an adder/subtractor 2 as the 1st adding/subtracting number via output terminals Q1-Q4. The 2nd adding/subtacting number is given to the input terminals A1-A4 of the adder/ subtactor 2 externally so to perform addition/subtraction in the complemental expression of. The result is outputted from S1-S4. The value of the most significant bit of the multiplier 1 is given to a carry input of C the adder/subtractor 2. That is, the most significant bit represents a positive or negative sign in the complemental expression of 2 and in cae of the negative sign, the bit goes to 1. Then, this bit (i.e., 1) is added to the least significant bit of the adder/subtractor 2. |
