CONTROL SYSTEM OF VECTOR PROCESSOR

摘要

PURPOSE:To execute efficiently a vector instruction train without logical discrepancy by changing the set value at decoding of a vector length change instruction at the beginning and changing the set value after the end of the execution of the instruction. CONSTITUTION:A data corresponding to an instruction is set to a register 15. The data in the register 15 has a part representing the length of the vector when it is corresponded to the vector length set instruction, and the vector length represented by the part is called NEWVL. When the instruction to be executed is the vector length set instruction, a vector length set circuit 19 sets the NEWVL in the register 15 to a vector length set register 18 based on a control command of an instruction transmission control section 20. The content of the register 18 is called OLDVL. An instruction fetched from a main storage is set to a register 16-1. A decoder 22 decodes a vector instruction of the register 16-1. The instruction control information obtained as a result is set to the register 17 and the instruction of the register 16-1 is set to the register 16-2.