| 摘要 |
<p>PURPOSE:To obtain a PAL type clock phase detector outputting clocks reducing jitter with a simple constitution by combining a differential signal generator, an integrator, delay circuits, and an adder. CONSTITUTION:A digital video signal is applied to the differential signal generator 10. The generator 10 inputs the digital video signal and adds a signal Pe-2 passed through two delay circuits 6, 7 to a signal -Pe passed through an inversion gate 8 by the adder 9. The circuit 10 finds out the difference between the data pe-2 of two samples before and the data Pe at the present time and outputs Pe-2-Pe. Subsequently, the integrator 11 integrates chrominance subcarriers out of a digital video signal only for a burst period. The integration is controlled by an integration controlling signal indicating the same period. The integrated output can be used as a phase difference signal. The adder 13 adds the phase difference signal to a signal obtaining by delaying the phase difference signal by one horizontal scanning period to obtain a composite difference signal.</p> |
