发明名称 RECEIVING BUFFER MANAGING SYSTEM
摘要 PURPOSE:To return a signal allowing the transmission of a packet to a transmission terminal, by adding the number of buffers decided with a preset window size to the occupied bufer number after confirming the fact that the said result of addition does not exceed the registered buffer number. CONSTITUTION:A packet exchange sets a call between terminals 2B and 2A in the normal packet procedure. When the terminal 2A receiving a data packet returns a packet RR possible for transmission, a packet analysis circuit 41 analyzes the returned transmissionable packet RR and starts a buffer managing circuit 43. The buffer managing circuit 43 extracts an occupied buffer number (q), a window size ws, a transmission sequence number ps, and a receiving sequence number pr, and calculates the data packet number transmitted consecutively by the terminal 2B, adds the number(ps-pr+1)subtracting the said result of calculation from the window size ws to the occupied buffer number (q), and discriminates whether or not the said result of calculation exceeds the registered buffer number (m), and when the number does not exceeds, the transmissionable packet RR is transferred to a packet transmission circuit 42 and transmitted.
申请公布号 JPS5970336(A) 申请公布日期 1984.04.20
申请号 JP19820181131 申请日期 1982.10.15
申请人 FUJITSU KK 发明人 MAKINO ATSUHIRO;SUZUKI TAKASHI;SONE YUKIO;MASUYAMA TOMOJI;KITANO MAKOTO
分类号 H04L12/56 主分类号 H04L12/56
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