发明名称 TEST SET FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To test a plurality of IC's under the state in which they are fixed to the same frame at the same time, and to shorten a test time by transmitting a fixed input to test circuits, checking the synchronous states through succeeding checks while transmitting the same test input data and deciding acceptables or defectives by each comparing the results with a reference value. CONSTITUTION:An input pattern data regarding some test item is transmitted over each driver-comparator 161-165 from a timing selector 13, and each converted into analog signals in the comparators and transmitted simultaneously over each IC 11-14 and 10. In this case, each IC and 10 generate test output signals, and the output signals are converted into digital signals by several driver-comparator 161-165 and memorized to output pattern data memories 181-185. In a digital comparator 20, a storage data from the output pattern data memory 185 for the standard sample IC10 and each storage data from the output pattern data memories 181-184 for test ICs are each compared simultaneously.
申请公布号 JPS5969941(A) 申请公布日期 1984.04.20
申请号 JP19820180911 申请日期 1982.10.15
申请人 TOSHIBA KK 发明人 TAKAAMA HITOSHI
分类号 G01R31/28;G06F11/273;H01L21/66 主分类号 G01R31/28
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