| 摘要 |
PURPOSE:To execute the extraction of the square root of two bits always at two cycles speedy by connecting the 1st and 2nd registers and shifting them simultaneously at the shift mode. CONSTITUTION:The contents of the 3rd register 3 are subtracted from the contents of the 1st register 1 by an arithmetic device 4. If the contents of the 1st register 1 are larger than that of the 3rd register 3, a carrying signal form the device 4 is outputted to a signal line 17 and the 1st selecting circuit 6 shifts the output from the device 4 to the upper direction by one bit. Since the status of the uppermost bit of the 2nd register 2 is inputted to the lowmost bit of the 1st register 1 through a signal line 15, the 1st selecting circuit 6 selects and outputs the data. Thus, the square root operation by the extraction of the square root of two bits can be operated at two cycles by using the small number of hardwares and the operation can be executed rapidly at a high speed. |
