| 摘要 |
PURPOSE:To attain high speed signal readout, by decreasing the number of switching times of a switch required for one scanning to less than conventional circuits by 1/10 or more with a signal readout from a common electrode so as to eliminate the effect of a matrix multi-layer wiring which is a cause for parasitic capacitance. CONSTITUTION:Analog switches 20-27, 28-35 are scanned with an individual electrode scanning circuit 44 and a common electrode scanning circuit 45, a signal charge stored at each picture element is converted into a voltage by using a preamplifier 14 and an integrator 16 and outputted through a sample-and-hold circuit (S/H) 18. Further, an analog switch 15 to reset the charge stored in the parasitic capacitance of the common electrode at the switching of the analog switches 28-35 at the common electrode side is connected to an input terminal of the preamplifier 14 so as to prevent the saturation of the preamplifier. Since the parasitic capacitance of the common electrode without any multi-layer wiring is very small in comparison with that of the individual wiring, spike noise is reduced. Since the switching of the analog switches 28-35 has only to be done at each common electrode, the number of times of switching is remarkably reduced. |
