发明名称 RETRIAL SYSTEM OF CONTROL MEMORY
摘要 PURPOSE:To make reexecution which starts at a microinstruction where an error occurs 100% possible without increasing the amount of hardware by using a service processor for microprogram loading. CONSTITUTION:If a detecting circuit 8 detects an error when a microinstruction 52 is read out of a control memory 3 to a microinstruction register 6, the execution of the instruction 52 is inhibited through the operation of an error holding register 9, gate 11, and FF 12. A control memory address corresponding to the instruction 52, on the other hand, is saved in a stand-by register 5. When receiving information on the error detection, the service processor 2 inputs the contents of a register 5, reads the instruction 52 out of a memory 1 by a specified address, and rewrites it in the control memory 3. Then, the processor 2 resets a register 9 and sets the address which is held in the register 5 in an address register 4 through a selector 13. Consequently, the instruction 52 is read out to the register 6 again and when it has no error, execution is restarted at the instruction 52.
申请公布号 JPS5968060(A) 申请公布日期 1984.04.17
申请号 JP19820178410 申请日期 1982.10.13
申请人 HITACHI SEISAKUSHO KK 发明人 HIRAMATSU MASATAKA;TAKEUCHI HIDENORI;ISHIYAMA AKIRA
分类号 G06F9/22;G06F11/14;G06F11/22 主分类号 G06F9/22
代理机构 代理人
主权项
地址