发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To offer a PLL circuit not unlocked even if an input signal is missing, by changing over the input signal and an output of a virtual signal generating circuit and inputting the result to a phase comparator with a dropout signal. CONSTITUTION:When a dropout is generated in the input signal I, a dropout detecting circuit 5 outputs a detecting signal D and a switching circuit 7 gives an output G of the virtual signal generating circuit 6 to the phase comparator 1. Mistead of the input signal I and the virtual signal, signal of NRZ waveform and EFM waveform may be used. Although the phase comparator 1 generates an error signal within one cycle since the phase between the input signal and the virtual signal G is shifted at the moment when the signal is switched, and then no frequency is shifted, the phase lock is performed immediately and the control voltage just before dropout is kept. The phase error within one cycle is generated similarly at the point of time of recovery after the end of dropout, but no frequency shift is generated at all and the synchronism is maintained.
申请公布号 JPS5967731(A) 申请公布日期 1984.04.17
申请号 JP19820179409 申请日期 1982.10.12
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SENOO TAKANORI
分类号 G11B20/14;H03L7/14 主分类号 G11B20/14
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