| 摘要 |
PURPOSE:To attain encoding, by converting an input m-bit data into an n-bit data, and detecting the bit inverting operation from the input m-bit data when there exists a part not in compliance with a prescribed rule in a continuous data up to a prescribed value. CONSTITUTION:An inverting code detecting section 30 detects that an input 4-bit data of the 2nd group is inputted, an output of an AND circuit 35 goes to logical ''1'', an output of a logical ''1'' AND gate of a Q output of a delay latch 36 goes to logical ''1'', and an inverting command TC is generated. Then, the bit train of ''0010001010010000'' stored tentatively in b'1-b'8, b1-b8 of a shift register 20 is inverted with bits of b2, b1, b'8 with the inverting command TC transmitted from the inverting code detecting section 30, and the b'1-b'8, b1-b8 become ''001000010001000''. Further, from the bit information of the right position of the shift register 20, an output data OUTD in 1-bit is outputted at each pulse of a clock CL'. |
