| 摘要 |
PURPOSE:To use effectively an interface between a channel controller and a channel, by incorporating a memory section storing a channel address, an input/ output device address, and interruption information in a channel controller. CONSTITUTION:A channel CH transmits an initial interruption request signal IT to a channel controller CHC. When a response RS from the device CHC exists, the channel CH reports the channel address, input and output device address and interruption information. The CHC gives an interruption request to the CPU and stores each information to a memory MEM. When the CPU informs the receivable state, the device CHC reports the memory MEM information to the CPU. Since the interruption request is transmitted and the receivable information is returned between the CPU and the CHC, the interruption request of the memory MEM of the CHC is increased/decreased with time. When the memory MEM is idle, the interruption is finished. |
