| 摘要 |
PURPOSE:To attain high speed processing by using in total the three stages of the processings as operating processing inverting one input data, data addition operating processing and an operating processing inverting the result of the addition or adding 1 to it. CONSTITUTION:A carry output C0 from the most significant digit and a carry input C1 to the least significant digit are coupled respectively to an adder 31 having the output of a data X and a data Y inverted by an inverter. The output of the adder 31 is transferred in common to an incrementer 32 and an inverter 36. If the carry output 34 is 0, an output A from the incrementer 32 is selected and when 1, an output B from the inverter 36 is selected and a resulting data Z is extracted from a multiplexer 33. The distance between the input X and the output Y is carried out with the three stages of the processings in total as the inverting processing by the inverter 35, the addition processing by the adder 31, and the processing of the incrementer 32 and the inverter 36 executed substantially at the same time to increase the speed remarkably. |
