| 摘要 |
PURPOSE:To realize a suitable circuit for control of data transfer among plural ring buses, and to improve the universality for a ring bus interface circuit, by providing a means which sets the priority on transfer ring request signals among plural sets of signals to select a pair of the request signals, and delivering a selection control signal. CONSTITUTION:A logical deciding circuit part, etc. are provided to have the priority on the transfer request signals among plural sets of signals and select one pair of the request signals to deliver a selection control signal. For instance, three sets of signals 11, 12 and 13 are supplied to a gate circuit part 1001, and at the same time the transfer request signal of each paired signals and a transfer destination disignating signal to a logical deciding circuit 1000 by signals 19, 20 and 21. Then the circuit 1000 delivers a selection signal 22 on the basis of a combination logic between the transfer destination designating signal of the paired signals selected by the priority on the transfer request signal, and the control signal of a signal 23. Then one of set signals 11, 12 and 13 is delivered to a set signal 17 by a gate circuit part 1001 and on the basis of the signal 22. Then the transfer acknowledge signal supplied from a signal 18 is delivered to one of signals 14, 15 and 16. |
