发明名称 SEQUENCE CONTROLLER
摘要 PURPOSE:To reduce the load of a master CPU and to improve the efficiency of a sequence controller by providing a slave CPU containing a storage part as well as a master CPU to perform the timer control of an I/O port or a soft flag, etc. CONSTITUTION:For the control of a copying machine, the 1st slave CPU21, the 2nd slave CPU22 and the 3rd slave CPU23 control the input/output of an operation part, an original reader and the input/output of a printer respectively. The CPUs 22 and 23 have four I/O expanders 31-37 and 41-47 respectively. A master CPU11 contains plural sequence control task groups and a real time monitor function which controls said task groups. An interruption is carried out by supplying an interruption signal 53 to the CPU11 from a program interval timer 51. While the interruption signal sent from the CPU21 and a drum clock pulse interruption signal 65 are supplied via a programmable interruption controller 61.
申请公布号 JPS5965306(A) 申请公布日期 1984.04.13
申请号 JP19820174496 申请日期 1982.10.06
申请人 CANON KK 发明人 YOSHIDA TADASHI
分类号 G05B15/02;G03G21/00;G05B19/02;G05B19/042;G05B19/05;G06F15/16 主分类号 G05B15/02
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