| 摘要 |
PURPOSE:To decrease the number of comparators, by connecting the comparators alternately between even and odd orders of both series of registers with clock signals after dividing the registers into two series, to arrange those comparators in order of scales and comparing the lower-order of both series to deliver them successively in order of smaller scales. CONSTITUTION:Plural registers are divided into two series, and 8 units of registers, for example, are arrayed in the state of T0. Then comparators C1 and C3 are connected between odd and even place registers at the left side, and a comparator C2 is connected between even and odd place registers by the indication of a control circuit (not shown in the diagram). Thus the registers are compared with each other, and the registers of larger values are moved to the upper part to obtain the state of T1. Then the connection between comparators is reversed, and the comparators are compared with each other with conversion of scales to obtain the state of T2. The same operation is repeated four times to obtain the state of T4, and the registers are arranged in order of scales at both sides. Then a comparator C4 compares the lowest stages of right and left sides and delivers them in order of smaller scale. With an example shown in the diagram, 1 and 2 are delivered from the right side and then 3 and 4 are delivered from the left side. Thereafter the registers are delivered in the same way. This enables a few comparator to perform sorting. |
