发明名称 PHASE LOCKED CONTROLLER
摘要 PURPOSE:To avoid variations of the control state due to a synchronism fault caused by noises, by deciding a synchronism fault state when the generating frequency of the synchronism fault signals in the input signal exceeds a prescribed level. CONSTITUTION:When an input signal is supplied, a closed holding circuit 11 works by a clock produced from a rise signal to keep a normal state after closing a solenoid switch 5 and forming a loop A. A synchronism fault detecting circuit 7 detects a synchronism fault state and delivers a synchronism fault signal to open the switch 5 via a pulse generating circuit 15 and an OR circuit 16. The output of the circuit 15 is also supplied to an input signal detecting circuit 17, and the output of the circuit 17 is fed to a delay circuit 18 and a counter 19. The output of the circuit 18 is supplied to a switch 14 to close the switch 5 again. While the counter 19 counts the frequencies of fault states and actuates an open holding circuit 12 and the switch 14 when the count value reaches a prescribed level. Then the switch 5 is duly opened for the first time.
申请公布号 JPS5964929(A) 申请公布日期 1984.04.13
申请号 JP19820176780 申请日期 1982.10.06
申请人 FUJITSU KK 发明人 KAWAGUCHI TOSHIO
分类号 H03L7/095;H03L7/14 主分类号 H03L7/095
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