SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To obtain the titled memory device of high speed and low power consumption by a method wherein a pre-word wire and a word wire are arranged in parallel with row direction and, at the same time, an AND gate is arranged in the center of each memory cell group. CONSTITUTION:When a memory cell is selected from a memory cell group 1a, the row address information of the memory cell group 1a to make access is decoded by a row decoder 4, and one of pre-word wires 15 is activated. Then, when a selective signal is applied to said memory cell group selection wire 14a, an AND gate 16a opens, and word wire 3a is activated. Accordingly, the column current flowing into the memory cell group 1a from the power source via a bit line runs into to the column located in the selected memory cell group 1a. Also when the AND gates 16a-16c, to be used for selection of memory cell groups, are arranged in the center of the memory cell groups 1a-1c, the resistance of the output terminal of the AND gates 16a-16c on a word wire 3a is reduced to half, thereby enabling to create an advantageous condition wherein the titled memory device can be operated at a high speed.