| 摘要 |
PURPOSE:To reduce the access time, by producing previously a parity bit based on the data read out of a storage part and using this parity bit for compensation in case an error is detected through checking. CONSTITUTION:The data read out of a storage part 1 is put on a bus 5' and sent to an error detecting circuit 2, a data correcting circuit 3 and a parity bit (PAB) producing circuit 4' respectively. When the circuit 2 detects an error, this error is informed to a processor via a signal line 8. At the same time, a code showing the position of the bit to be corrected is sent to a bus 7 to inform the error also to the circuit 4'. The circuit 3 inverts the errorneous bit to be corrected with the fed data. The circuit 4' produces previously a PAB based on the data given from the part 1 and inverts the PAB into a correct one when the detection of an error is informed. The correct PAB is added to the data corrected by the circuit 3 and then transmitted 6. In such a way, the access time can be reduced. |
