| 摘要 |
PURPOSE:To reduce the plane-like area of a memory cell and an element isolation region by forming a capacitance to the side surface of a groove bored to the surface of an Si substrate and forming the isolation region to a groove bottom and the side surface of one part. CONSTITUTION:An Si3N4 mask 12 is executed on an SiO2 thin-film 11 on the P type Si substrate 1, and a channel stopper 201 and a SiO2 thick film 20 to which a bird beak is formed are formed according to a predetermined method. A CVD SiO2 22 is superposed and masked with a resist 23, a groove 24 is formed through reactive sputtering etching by CF4+H2, and an inclined plane 25 with a vertical surface 26 and a bird beak residual section 202 is shaped. The mask 23 is removed and the surface is coated with CVD Si3N4 27, and a channel stopper 29 is formed left only on a vertical surface through reactive sputtering etching. The SiO2 22 is removed, and the surface is coated with an SiO2 30 through wet oxidation. The films 11, 12, 27 are removed through etching, the groove is filled with P added poly Si 33 through a thermal oxide film 32, and the semiconductor device with the capacitance isolated by the inclined plane and bottom of the groove is completed through patterning by a resist mask 34. |
