| 摘要 |
PURPOSE:To contrive reduction in chip size and improvement in the degree of integration by a method wherein the conductive layer, to be used for the gate electrode composed of a polycrystalline silicon pattern and the like, and the second conductive layer are connected to the desired point, and the connection of the conductive layer to be used for the gate electrode and the third conductive layer is made by connecting the third conductive layer to the second conductive layer. CONSTITUTION:A P-type diffusion layer (source) 1a is connected to the first Al 12 by a contact hole 23, and an N-type diffusion layer (source) 5a is connected to the first Al 13 by a contact hole 24. Also, P-type and N-type diffusion layers (drain) 1b and 5b are connected to the second Al 18 by contact holes 25 and 26 and the first through holes 27 and 28 respectively. Moreover, the first Al 12 and 13 are connected to diffusion layers 31 and 32 by contact holes 29 and 30, and also a polycrystalline silicon pattern 9 is connected to the second Al 19 through a contact hole 33 and the first through hole 34. As a result, an inverter circuit, having a polycrystalline silicon pattern 9 as an input terminal and the second Al 18 as an output terminal, is formed. |
