| 摘要 |
PURPOSE:To follow up jitter with the wide permissible width of phase jitter and speed over a wide range by using an optimum clock out of four clocks obtained by dividing one period of data transmission frequence by 4 to latch an input. CONSTITUTION:An input signal is divided into a, b and c at its changing points in the division of one period of reference frequency by jitter with 3/4 width of one period of the reference frequency. At the change of an input, an input change detecting circuit generates a pulse with the pulse width corresponding to the delayed value of a delay circuit 106. D types FFs 111, 112 latch the values of clocks phi1, phi2 at the leading edge of an output of the input change detecting circuit. The values of the clocks phi1, phi2 can discriminate the changing points a, b, c, or d of the input signal. A selector 120 selects the clock to enter an input. |
