发明名称 DELAY CIRCUIT
摘要 PURPOSE:To obtain a circuit forming the time delay of an analog signal by that of a digital signal unexpensively by using a selecting circuit, an adder, a counting circuit, and a storage circuit. CONSTITUTION:An analog input signal 1 is sampled and coverted into a digital signal by analog/digital converting circuit 2. The digital signal is stored in the storage circuit 6. The selecting circuit 8 selects the storing address of the storage circuit 6 to the data of the counting circuit 11 and then reads out the digital signal from the storage circuit 6. The digital/analog converting circuit 3 converts the digital signal into an analog output signal 4. The selecting circuit 8 selects the storing address of the storage circuit 6 at that time to the data obtained by adding the data of the counting circuit to a delay signal by the adder 9. Said cycle is repeated.
申请公布号 JPS5963813(A) 申请公布日期 1984.04.11
申请号 JP19820173747 申请日期 1982.10.02
申请人 KANEMATSU KAZUYOSHI 发明人 KANEMATSU KAZUYOSHI
分类号 H03H11/26;H03H17/00;H03H17/08 主分类号 H03H11/26
代理机构 代理人
主权项
地址