发明名称 ERROR DETECTING SYSTEM OF INFORMATION PROCESSING SECTION
摘要 PURPOSE:To recognize the location of a failure by providing a driver with gate transmitting data, a receiver receiving the data, and a parity checker connected to the output of the receiver to check the data transmitted to other device from a bidirectional data bus. CONSTITUTION:A processor and an input/output device are connected respectively to a channel CH via a bidirectional bus BDB, drivers DV3, 4 and receivers RV3, 4 are connected to the channel CH of the bus BDB and gate signals G3, G4 are impressed respectively to the drivers DV3, DV4. Further, parity checkers PC3, PC4 are provided between the receivers RV3, 4 and a data register DRG and the register DRG connects the drivers DV3, 4 respectively. Then, the parity of the transmission data from the processor or the input/output device is checked by the checkers PC3 or 4 to detect the failure in detail.
申请公布号 JPS5962935(A) 申请公布日期 1984.04.10
申请号 JP19820172294 申请日期 1982.09.30
申请人 FUJITSU KK 发明人 TANIGUCHI HARUMASA
分类号 H03M13/00;G06F11/273;G06F13/00 主分类号 H03M13/00
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