| 摘要 |
PURPOSE:To reduce input capacity, and to manufacture a J-FET of high performance with high yield by a method wherein channel width is prescribed by a silicon oxide region formed on the surface of a silicon substrate put between a source and a drain. CONSTITUTION:Width (height H) of a channel part 6 is prescribed. The silicon oxide region 7 is formed on the surface of an n<+> type layer accoding to oxygen ion implantation, the P<+> type substrate 1 acts as the gate electrode, and a depletion layer 9 is generated at the channel part from the p<+> type substrate side by application of a gate voltage to control a source.drain current. By providing the oxide region in place of a p<+> type diffusion layer provided as the gate in the past, p<+>-n junction according to the gate on the surface side is not generated, and input capacity is constructed of only junction capacity on the substrate side. |
