| 摘要 |
PURPOSE:To decrease the number of stages of a shift register of a solid-state TV pulse generating circuit, by applying a different clock frequency between an m-bit section and an n-bit section among (m+n)-bit shift registers. CONSTITUTION:The horizontal frequency is produced at a ring counter circuit using the shift registers and pulses with shifted phase from each state of the shift registers are combined, allowing to form all required pulses for the camera. A high frequency pulse is formed at an oscillating circuit 31 and frequency- divided into two at a frequency division circuit 90. A pulse generated at an input pulse generating section 41 is inputted to a shift register 33a of 189 stages determining the video image period and a shift register of 77 stages determining the horizontal blanking period. Taking the clock of the former shift register as 3.58MHz and the latter as 7.2MHz, the period of pulse required for one circulation is one horizontal scanning period, and the number of stages is decreased less than a circuit driving all shift registers in the same frequency. |
