发明名称 FORMATION OF GATE STRUCTURE
摘要 PURPOSE:To obtain MONOS structure having a stable channel forming voltage by a method wherein a first oxide film to act as the gate insulating film and a silicon nitride film are formed in a transistor formation programing region on a silicon substrate, field oxide films are formed at the places other than the programing region, and at the same time, a second oxide film of silicon oxide is provided on the silicon nitride layer. CONSTITUTION:The first oxide film 2 is formed on the surface of the silicon substrate 1, and the silicon nitride film 3 is formed thereon. A resistor 4 is provided on the transistor formation programing region in succession, and the silicon nitride layer 3 is removed according to plasma etching. Then the resistor 4 is removed, and the field oxide films 5 are generated at the places other than the programing region according to steam oxidation. At this time, the surface of the silicon nitride layer 3 is also oxidized to form the second oxide film 6 consisting of SiO2. After a high melting point metal layer is formed on the second oxide film thereof, the high melting point metal layer, the second oxide film and the silicon nitride layer are etched to obtain a gate region forming shape, and the gate part of the FET is formed.
申请公布号 JPS5961966(A) 申请公布日期 1984.04.09
申请号 JP19820172900 申请日期 1982.09.30
申请人 SANYO DENKI KK 发明人 TAINO NOBUYASU
分类号 H01L29/78;H01L29/423;H01L29/43;H01L29/49;H01L29/792 主分类号 H01L29/78
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