| 摘要 |
PURPOSE:To improve the resolution of a D/A conversion circuit by providing a pulse adder circuit outputting an output pulse of a gate circuit and a pulse to be counted to the least significant bit of a counter. CONSTITUTION:A D/A converting circuit 2 has less bit number than that of a deviation counter 1 by 2, the both are connected sequentially from the most significant bit and the low-order 2-bit of the deviation counter 1 is opened. An addition/subtraction changeover counter 3 counts a high speed pulse faster than a command pulse and the output of the most significant bit is outputted to the deviation counter 1 as an up signal. An inverter 5 inverts the high speed pulse, a NAND gate 6 ANDs the output of the low-order 2 bit the counter 3 and outputs the result inversely. An AND gate 7 ANDs the output of the inverter 5 and the output of the NAND gate 6 and outputs the result as a clock pulse CP. A pulse adder circuit 8 outputs a pulse train sequentially comprising clock pulses CP where the pulse of the low level of the output of the NAND gate 6 is missing.
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